G - Physics – 06 – F
Patent
G - Physics
06
F
356/117
G06F 11/00 (2006.01)
Patent
CA 1309511
ABSTRACT OF THE DISCLOSURE In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. zero-delay coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.
577456
Agarwal Vinod Kumar
Nadeau-Dostie Benoit
Wilcox Philip Stanley
Adams Patent & Trademark Agency
Agarwal Vinod Kumar
Nadeau-Dostie Benoit
Nortel Networks Limited
Wilcox Philip Stanley
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