Integrated circuit in complementary circuit technology...

Details Integrated circuit in complementary circuit technology... Integrated circuit in complementary circuit technology...

G - Physics

05

F

356/125, 328/200

G05F 3/20 (2006.01) H01L 27/02 (2006.01)

Patent

CA 1275457

Abstract Of The Disclosure An integrated circuit executed in complementary circuit technology, has a substrate bias generator (16) which connects the substrate (1) to a substrate bias. A well (2) of opposite conductivity is inserted into the substrate (1), and FETs with complementary channels are inserted into the substrate (1) and into the well (2), respectively. The source regions (3) of the FET's of first conductivity lie at ground potential. In order to avoid latch-up effects, the output (17) of the substrate bias generator (16) is connected via an electronic switch (S1) to a circuit point (8) lying at ground potential, the switch being driven via a time-delay circuit (24) charged with the supply voltage so that it opens with a prescribed time-delay after the supply voltage is applied.

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