Integrated circuit layout utilizing separated active circuit...

Details Integrated circuit layout utilizing separated active circuit... Integrated circuit layout utilizing separated active circuit...

H - Electricity

05

K

356/12

H05K 1/16 (2006.01) H01L 23/522 (2006.01) H01L 23/528 (2006.01) H01L 27/118 (2006.01)

Patent

CA 1102009

INTEGRATED CIRCUIT LAYOUT UTILIZING SEPARATED ACTIVE CIRCUIT AND WIRING REGIONS Abstract of the Disclosure A planar semiconductor integrated circuit structure in which the layout design of the wiring channels on the semiconductor surface is considered separately from the layout design of the active circuits within the semiconductor. In this way, the density and/or placement of the wiring channels on the surface of the chip may be varied so as to increase the utilization of the wiring channels.

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