Integrated circuit memory cell

G - Physics – 11 – C

Patent

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352/82.1

G11C 11/40 (2006.01) G11C 11/411 (2006.01) H01L 27/00 (2006.01) H01L 27/102 (2006.01) H03K 3/286 (2006.01)

Patent

CA 1042101

INTEGRATED CIRCUIT MEMORY CELL Abstract of the Disclosure A cell for an integrated circuit memory is formed of two interconnected identical halves. Each such half is integrally formed without surface metal inter- connections. The memory is fabricated from a semi- conductor body which comprises an epitaxial layer of one conductivity type overlying a semiconductor substrate of the opposite type. Each half comprises a vertical npn transistor having the collector thereof at the exposed surface of the epitaxial layer and a lateral current source transistor. The collector region of each vertical transistor has two metal contacts, one to form a Schottky diode to couple to a bit line, and one to form an ohmic connection for crosscoupling of the two halves. Power is distributed by a line diffused in the epitaxial layer which line comprises the emitters of the lateral current source transistors and power is returned through word lines which are formed in the substrate of the body prior to growth of the epitaxial layer.

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