Integrated circuit memory device

Details Integrated circuit memory device Integrated circuit memory device

H - Electricity

01

L

H01L 27/112 (2006.01) G11C 11/56 (2006.01) G11C 17/00 (2006.01)

Patent

CA 2154802

The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per output. Each of the plurality of outputs is connected to one of a plurality of memory cells. Each memory cell comprises an impedance element, its impedance value representative of the data value stored therein. All of the memory cells are thereafter connected to a sum line and a read out circuit. When the signal source provides one of the sequence signals to one of the memory cell impedance elements, it affects the signal on the sum line in a manner that is related to the impedance value of the memory cell. By applying each signal in the sequence to a different impedance element, the voltage on the sum line is directly affected by each of the impedance elements in sequence. The read out circuit transforms the read out circuit voltage into a voltage level proportional or otherwise indicative of each impedance value, and thus the stored data, in sequence.

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