Integrated circuit planarizing process

Details Integrated circuit planarizing process Integrated circuit planarizing process

H - Electricity

01

L

204/96.05

H01L 21/70 (2006.01) H01L 21/3105 (2006.01) H01L 21/311 (2006.01) H01L 21/312 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1169022

ABSTRACT OF THE DISCLOSURE A planarizing process for producing a passivation or insulating layer immediately underlying an upper metallized layer on the surface of an integrated circuit having very large radius of curvature steps, thus providing a reliable base for the metallized layer. The process is comprised of the steps of depositing and defining first metal conductors on the surface of an integrated circuit, depositing a first dielectric layer over the surface of the integrated circuit including the conductors, the dielectric layer being comprised of material selected from the group comprised of silicon dioxide and silicon nitride, depositing and polymerizing a layer of negative isoprene resist over the surface of the dielectric layer, etching the surface of the isoprene and dielectric layers to a predetermined thickness over the metal conductors, cleaning the etched surface, and depositing a second dielectric layer over the surface selected from the group comprised of silicon dioxide and silicon nitride, whereby a surface having very large radius of curvature steps over the metal conductors is produced.

401226

Affiliated with

Also associated with

Rating

Integrated circuit planarizing process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit planarizing process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit planarizing process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1240843