Integrated circuit sampled-and-hold phase detector with...

Details Integrated circuit sampled-and-hold phase detector with... Integrated circuit sampled-and-hold phase detector with...

G - Physics

01

R

G01R 27/00 (2006.01) G01R 27/28 (2006.01) H03D 13/00 (2006.01)

Patent

CA 2075127

A sample-and-hold phase detector comprises a first charge/discharge circuit for charging a first storage capacitor with a constant current for a duration corresponding to a phase difference between an input pulse and a reference pulse and discharging it after it is sampled. A first sample-and- hold circuit samples the voltage developed in the first storage capacitor to represent the phase difference between the input pulse and the reference pulse. A second charge/discharge circuit periodically charges a second storage capacitor with a constant current for a fixed time interval and discharges it after it is sampled. A second sample-and-hold circuit samples the voltage developed in the second storage capacitor. A current setting circuit, in which a current setting resistor is provided, is connected to both charge/discharge circuits to determine their constant charging currents. A differential integrator provides differential integration on the voltage from the second sample-and-hold circuit with respect to a reference voltage to control the current setting circuit in a feedback loop.

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