Integrated circuit testing system and method

Details Integrated circuit testing system and method Integrated circuit testing system and method

G - Physics

01

R

G01R 31/28 (2006.01) G01R 31/30 (2006.01) G01R 31/303 (2006.01) G01R 31/317 (2006.01) G01R 31/3187 (2006.01) G01R 31/3193 (2006.01)

Patent

CA 2364421

A system and method for testing an integrated circuit at low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

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