Integrated circuit using complementary junction field effect...

Details Integrated circuit using complementary junction field effect... Integrated circuit using complementary junction field effect...

H - Electricity

01

L

H01L 31/111 (2006.01) H01L 21/337 (2006.01)

Patent

CA 2626706

This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

L'invention concerne un procédé de fabrication de circuits logiques complémentaires à l'aide de transistors à effet de champ à jonction en silicium. La présente invention convient idéalement pour des dimensions fortement submicroniques, de préférence inférieures à 65 nm. La base de cette invention est un transistor complémentaire à effet de champ à jonction fonctionnant en mode enrichissement. Les performances en vitesse-puissance des JFET deviennent comparables à celles des dispositifs CMOS dans les dimensions inférieures à 70 nanomètres. Cependant, la tension maximale d'alimentation pour les JFET est encore limitée à une valeur inférieure au potentiel incorporé (d'une chute de tension de diode). Pour satisfaire aux exigences de certaines applications nécessitant une interface vers un circuit externe piloté à des niveaux de tension plus élevés, cette invention comprend les structures et procédés pour fabriquer des dispositifs CMOS sur le même substrat que les dispositifs JFET.

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