Integrated circuit with memory self-test

Details Integrated circuit with memory self-test Integrated circuit with memory self-test

G - Physics

11

C

352/82, 324/58.1

G11C 29/00 (2006.01) H01L 27/04 (2006.01)

Patent

CA 1299289

- 10 - INTEGRATED CIRCUIT WITH MEMORY SELF-TEST Abstract A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing ease of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

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