Integrated clock drive circuit

Details Integrated clock drive circuit Integrated clock drive circuit

H - Electricity

03

K

328/87

H03K 5/135 (2006.01) H04L 7/02 (2006.01) H04L 7/027 (2006.01) H04L 7/04 (2006.01)

Patent

CA 1109931

AN INTEGRATED CLOCK DRIVE CIRCUIT by Jay A. Thomas and Victor J. Stalick, Jr. ABSTRACT OF THE DISCLOSURE A buffer amplifier, which prevents loading of the input signal, accepts at its input an amplified and equalized pseudo-ternary signal. The output of the buffer amplifier is a-c coupled to the input of a precision differential amplifier, from which two output signals are obtained. One said output signal is representative of the positive pulses and the other said output signal is representative of the negative pulses of the pseudo-ternary signal. These two output signals are both applied to the inputs of a peak detector and a slicer. The d-c output of the peak detector is also applied as one input to the slicer. Separate outputs are obtained from the slicer, one each for the positive and negative pulse inputs, and these two outputs are summed, and the summed output is then amplified to provide a clock-driver output. -- 1 --

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