Integrated high-speed serial interfaces

H - Electricity – 03 – M

Patent

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Details

H03M 9/00 (2006.01)

Patent

CA 2245760

A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

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