H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/308 (2006.01) H01L 21/311 (2006.01) H01L 21/768 (2006.01)
Patent
CA 2193905
A method of fabricating a semiconductor device includes etching holes through atleast one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned, and contact or via holes are etched through the patterned hard mask to reach the underlying structure
Méthode de fabrication d'un dispositif semi-conducteur comprenant des trous d'attaque jusqu'à la structure sous-jacente, à travers au moins une couche déposée. Un masque dur est déposé sur une surface supérieure; des motifs sont gravés sur le masque et des trous de contact ou des trous traversants sont pratiqués à travers le masque dur gravé pour atteindre la structure sous-jacente.
Azelmad Abdellah
Ouellet Luc
Marks & Clerk
Mitel Corporation
Zarlink Semiconductor Inc.
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