G - Physics – 06 – F
Patent
G - Physics
06
F
354/147, 354/167
G06F 7/52 (2006.01) G06F 7/544 (2006.01) G06F 15/80 (2006.01) G06F 17/14 (2006.01) G06F 17/15 (2006.01)
Patent
CA 1196422
22762-401 Abstract The invention provides a digital data processor which has been systemetised down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency. Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers. Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven. JX/6089/05
409023
Mccanny John V.
Mcwhirter John G.
Wood Kenneth W.
Fetherstonhaugh & Co.
National Research Development Corporation
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