Inter and intra priority resolution network for an...

G - Physics – 06 – F

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354/234

G06F 13/36 (2006.01) G06F 13/37 (2006.01)

Patent

CA 1314332

ABSTRACT OF THE DISCLOSURE A data processing system includes a plurality of units including a bus interface unit (BIU), each of which couple in common to different positions along an asynchronous common bus. The BIU couples to a plurality of local units which connect to a high speed local bus. The asynchronous common system bus includes a distributed tie-breaking priority which consists of a plurality of like priority network sections. The BIU includes a priority resolver which incorporated the priority network section having the highest priority access to the asynchronous bus. The priority resolver includes a local priority resolver circuit for resolving priorities between local requesters within a minimum amount of time. The priority network section and local priority resolver circuit are interconnected so that the signal generated by the network section request circuits to request use of the asynchronous bus is applied to the local priority resolver circuit and to the common bus at the same time. This permits both bus resolution cycles for resolving external and internal requests to proceed in parallel. Thus, access to the system bus will always be resolved within a single bus resolution cycle of operation.

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