Interconnection networks

Details Interconnection networks Interconnection networks

H - Electricity

04

L

354/233

H04L 12/28 (2006.01) G06F 15/16 (2006.01) G06F 15/173 (2006.01)

Patent

CA 1323447

INTERCONNECTION NETWORKS ABSTRACT OF THE INVENTION A network of interconnected processors is formed from a vertex symmetric graph selected from graphs rd(k) with degree d, diameter k, and (d+l)!/(d-k+l)! processors for each d?k and rd(k.-l) with degree d-l, diameter k+l, and (d+l)!/(d-k+l)! processors for each d?k?4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors. where each processor has one less channel than the selected number of letters forming the sequence. Where a network rd(k.-l) is provided, no processor has a channel connected to form an edge in a direction .delta.l. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations.

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