Interface arrangement for buffering communication...

Details Interface arrangement for buffering communication... Interface arrangement for buffering communication...

H - Electricity

04

Q

344/25

H04Q 11/04 (2006.01) H04Q 11/06 (2006.01)

Patent

CA 1215451

AN INTERFACE ARRANGEMENT FOR BUFFERING COMMUNICATION INFORMATION BETWEEN A TRANSMITTING AND RECEIVING STAGE OF A TIME-SPACE-TIME DIGITAL SWITCHING SYSTEM ABSTRACT OF THE DISCLOSURE An interface arrangement is shown compensating for timing delays during transmission of communication information between a transmitting and receiving stage of a T-S-T digital switching system. The arrangement includes a buffer at the receiving stage having first and second storage files. During a first time slot communication information is written in the first using control signals transmitted along with the communication information while simultaneously the second file is read using a local control signal. In the subsequent time slot the second file is written to and the first file is read, providing a one time slot slip between the transmitting and receiving stages.

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