Interface for controlling information transfers between main...

Details Interface for controlling information transfers between main... Interface for controlling information transfers between main...

G - Physics

06

F

354/245

G06F 13/00 (2006.01) G06F 12/04 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1165458

ABSTRACT OF THE DISCLOSURE In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to re- tain the integrity of the cache memory in the central subsystem.

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