G - Physics – 06 – F
Patent
G - Physics
06
F
354/233
G06F 13/00 (2006.01) G06F 9/445 (2006.01) G06F 13/12 (2006.01) G06F 15/173 (2006.01) G06F 15/177 (2006.01) G11C 7/00 (2006.01)
Patent
CA 1183273
Abstract of the Disclosure An interface mechanism between a pair of processors such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40). The interface utilizes a set of data structures employing a dedicated communications region (80A) in host memory (80). There are two layers to the interface - a transport mechanism and a port; the latter is hardware for communicating via the transport mechanism and a process implementing a set of rules governing those communications. Commands and responses are communicated as packets over the host's I/O bus (60), to and, from the communications region (30A) through a pair of ring-type queues (80D and 80E). These rings, and the rules governing their operation, permit the host and controller processors to operate at their own speeds, without creating race conditions of other timing problems while obviating the need for a hardware interlock capability on the I/O bus. The ring entries point to other locations in the communications region where commands and responses are placed. The filling and emptying of ring entries is controlled through the use of an "ownership" byte or bit Fig. 8, 278; Fig. 313, 133, 135, 137, 139) associated with each entry (Fig. 38, 132, 134, 136, 138). The ownership bit is placed in a first state when the message source (i.e., controller or host) has filled the entry and in a second state when the entry has been emptied by its receiver. A message oriented credit system provides flow control and prevents more packets being sent than a ring can accept. Interrupt generation is reduced because strings of commands and responses can be communicated without need for interrupting the host processor for each one. The interface mechanism requests interrupts primarily only when its command ring undergoes a state change from full to not-full and when its response ring undergoes a state change from not-empty to empty. A "FLAG" bit in a preselected register controls the generation of interrupt requests. During a multi-step initialization procedure, the integrity of the communications path between host and controller is checked out. In particular, the communications path includes a register and information is written to and read from the register to vecify correct operation of each bit of the register. As part of the write-read processs, certain host-specific parameters, such as the sizes of the ring-type queues and their starting addresses is sent from the host to the controller. Capability is shown also for allowing repeated access to the same host memory location for successive reads, writes, or any combination of the two. With bus adapters which impose rigid sequencing rules which do not allow reads and writes to be mixed, the adapter channel is pruged between successive accesses to the same location. The port requests the purge and it is executed by the host.
412726
Gardner Edward A.
Grace William A.
Keck Dale R.
Lary Richard F.
Rubinson Barry L.
Digital Equipment Corporation
Smart & Biggar
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