Interfacing device to extract m sets of bits out of n sets...

Details Interfacing device to extract m sets of bits out of n sets... Interfacing device to extract m sets of bits out of n sets...

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 19/20 (2006.01) H04L 12/56 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2228059

An interfacing device (INT) which e-xtracts M outgoing sets of bits (OS1, OS2,..., OSM) out of N incoming sets of bits (IS1, IS2, ... ISN), M being smaller than N, includes: a. an incoming register (IR) wherein the N incoming sets of bits (IS1, IS2, ..., ISN) are temporarily stored; and b. a selector (SEL) comprising a multiplexer bank (MUX) with M multiplexers (MUX1, MUX2, ..., MUXM) each having N-M+ 1 inputs and one output,and a control unit (CTRL) for the multiplexer bank (MUX). The distinct sets of N-M+ 1 incoming sets of bits that are applied to distinct multiplexers overlap and the control unit (CTRL) can control the multiplexers (MUX1, MUX2 ..., MUXM) so that an appropriate order is respected by the outgoing sets of bits (OS1, OS2, ..., OSM).

Dispositif d'interface (INT) qui extrait des jeux de bits de sortie M (OS1, OS2, ..., OSM) de jeux de bits d'entrée N (IS1, IS2, ..., ISN), M étant plus petit que N. Ce dispositif comprend : a) un registre d'entrée (IR) dans lequel les jeux de bits d'entrée N (IS1, IS2, ..., ISN) sont temporairement mémorisés; b) un sélecteur (SEL) comprenant une banque de multiplexage (MUX) avec des multiplexeurs M (MUX1, MUX2, ..., MUXM) ayant chacun des entrées N-M+1 et une sortie, ainsi qu'une unité de commande (CRTL) pour la banque de multiplexage (MUX). Les jeux distincts de jeux de bits d'entrée N-M+1 qui sont appliqués à des multiplexeurs distincts se chevauchent, et l'unité de commande (CTRL) peut commander les multiplexeurs (MUX1, MUX2, ..., MUXM), afin qu'un ordre approprié soit respecté par les jeux de bits de sortie (OS1, OS2, ..., OSM).

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