Interference suppression

Details Interference suppression Interference suppression

H - Electricity

04

B

340/72

H04B 15/00 (2006.01) H04B 3/30 (2006.01) H04L 25/02 (2006.01)

Patent

CA 2036865

ABSTRACT Interference Suppression System A line driver 12 is coupled by a pair of signal lines 10, 11 to a receiver 13. Preprocessing circuitry 18, for processing signals arriving on the pair of signal lines at the receiver, includes regulating means (Fig. 2) for regulating the potential between the signal lines between predetermined limits and thereby modifying the sensitivity of the system to compensate for changes in line conditions and reject interference when the line driver is powered down. The regulating means comprise: bias means Ql-Q3, Q12 for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away prom the triggering voltage level so that it is not triggered by noise; and bias limiting means Q6-Q7, Q9-Q11 responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level. Figs. 1, 2

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