Interleaved wordline architecture

Details Interleaved wordline architecture Interleaved wordline architecture

G - Physics

11

C

G11C 5/08 (2006.01) G11C 5/06 (2006.01) G11C 8/14 (2006.01) G11C 11/4097 (2006.01) H01L 21/8242 (2006.01) H01L 27/108 (2006.01) H01L 27/02 (2006.01)

Patent

CA 2340985

A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance. Hence the memory cell architecture of the present invention occupies less area, and operates with faster speed than memory cell architectures of the prior art.

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