Interlock control of asynchronous data transmission between...

Details Interlock control of asynchronous data transmission between... Interlock control of asynchronous data transmission between...

G - Physics

06

F

340/88

G06F 15/18 (2006.01) G06F 13/364 (2006.01) G06F 15/167 (2006.01)

Patent

CA 1113172

TITLE INTERLOCK CONTROL OF ASYNCHRONOUS DATA TRANSMISSION BETWEEN A HOST PROCESSOR AND A PLURALITY OF MICROPROCESSORS THROUGH A COMMON BUFFER ABSTRACT An interlock circuit and method providing for control of asynchronous data transfer between a host pro- cessor and a plurality of microprocessors through a common buffer. The interlock circuit consists of an interconnection of latching means arranged so that the first processor initiating a transfer request inhibits all remaining pro- cessors from activating their respective transfer requests. Each processor upon terminating a data transfer clears its associated transfer request. The host processor can clear all transfer requests upon command.

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