Intermediate decimal correction for sequential addition

Details Intermediate decimal correction for sequential addition Intermediate decimal correction for sequential addition

G - Physics

06

F

354/204

G06F 1/00 (2006.01) G06F 7/50 (2006.01)

Patent

CA 1246746

Abstract Appartus is provided to restore an excess six correct to every digit of an intermediate result which did overflow during the previous addition operation during a sequence of repeated BCD addition operations. A carry register is defined to store and feedback logical signals indicative the occurance of an overflow event.

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