Internal row sequencer for reducing bandwidth and peak...

G - Physics – 09 – G

Patent

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G09G 3/20 (2006.01) G09G 3/36 (2006.01)

Patent

CA 2310257

A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.

L'invention concerne un circuit pilote d'afficheur comprenant un séquenceur de lignes de mots servant à fournir une série d'adresses lignes, et un décodeur de lignes servant à décoder chacune des adresses lignes et à confirmer les signaux d'écriture aux terminaux correspondants d'une pluralité de terminaux de sortie. Un séquenceur de chemins de données facultatif fournit une série d'adresses de chemins utilisées par un routeur données facultatif de manière à acheminer les données vers des sous-lignes particulières d'un afficheur. En outre, un séquenceur de sous-lignes facultatif fournit, à un décodeur de sous-lignes facultatif, une série d'adresses de sous-lignes, lequel décodeur décode chacune des adresses de sous-lignes et confirme les signaux d'écriture aux terminaux correspondants d'une pluralité de terminaux de sortie.

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