Interprocessor communication and synchronization

G - Physics – 06 – F

Patent

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354/233, 340/84

G06F 13/00 (2006.01)

Patent

CA 1170740

- 19 - Case 4319 INTERPROCESSOR COMMUNICATION AND SYNCHRONIZATION ABSTRACT OF THE DISCLOSURE A system for synchronizing communications between a network of processors with a distributed memory is disclosed. A plurality of microprocessors (10), each having a dedicated memory module (12) associated therewith, are interconnectable with memory modules (12) dedicated to the other microprocessors (10) in the net- work for communication over a common bus (16). Each microprocessor has access to all memory locations in its dedicated memory module (12) and a portion of the memory locations in the memory modules (12) dedicated to the other microprocessors (10) in the network. A specific memory location in this portion of memory locations in each memory module (12) is designated as a test-and- set location and its contents are modifiable by being accessed by a microprocessor so as to indicate to the other microprocessors in the network that the memory module is being accessed and unavailable for communica- tion from other microprocessors in the network. In this manner, communication between the microprocessors (10) and the memory modules (12) can be synchronized and regulated.

381873

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