G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/24 (2006.01) G06F 11/34 (2006.01)
Patent
CA 2152110
Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are re-coding their algorithms to exploit memory systems. All of these groups need empirical data on memory behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. By augmenting a cache miss counter with a compare register and interrupt line such that the processor is interrupted when the counter matches the compare value, we can sample system state and develop cache miss profiles that associate cache misses with specific processes, procedures, call stacks, addresses, or user defined aspects of system state. This idea is implemented in the Mprof prototype that profiles data stall cycles, first level cache misses, and second level misses on the sun Sparc 10/41. Simple case studies are provided to illustrate Mprof's features.
Agrawal Prathima
Goldberg Aaron Jay
Trotter John Andrew
At&t Corp.
Kirby Eades Gale Baker
LandOfFree
Interrupt-based hardware support for profiling system... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interrupt-based hardware support for profiling system..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interrupt-based hardware support for profiling system... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1708165