Interrupt handling in a multiprocessor computing system

Details Interrupt handling in a multiprocessor computing system Interrupt handling in a multiprocessor computing system

G - Physics

06

F

354/230.85

G06F 13/26 (2006.01)

Patent

CA 1265624

ABSTRACT OF THE DISCLOSURE A multiprocessor computing system is disclosed which includes a system bus, a plurality of processing units and a plurality of synchronous input/ouput channel controllers. A plurality of priority lines each corresponding to a processing unit are provided through each input/output channel controller in order of priority. A synchronizing signal is generated at the same time in each input/output channel controller in response to the end of an address phase on the system bus. A latch is provided in the input/output controllers which responds to the synchronizing signal by storing the condition of the priority lines and whether an interrupt is pending. In response to a broadcast interrupt origin request instruction from a processing unit, all input/output channel controllers will respond at the same time but only the one with the priority interrupt for the requesting processing unit gives a non-zero response.

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