Interrupt mechanism for multi-microprocessing system having...

Details Interrupt mechanism for multi-microprocessing system having... Interrupt mechanism for multi-microprocessing system having...

G - Physics

06

F

354/230.82

G06F 13/24 (2006.01) G06F 15/16 (2006.01) G06F 15/17 (2006.01)

Patent

CA 1241762

INTERRUPT MECHANISM FOR MULTI-MICROPROCESSING SYSTEM HAVING MULTIPLE BUSSES Abstract of the Disclosure A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.

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