Introducing processing delay as a multiple of the time slot...

Details Introducing processing delay as a multiple of the time slot... Introducing processing delay as a multiple of the time slot...

H - Electricity

04

B

H04B 1/18 (2006.01) H04B 7/08 (2006.01) H04L 1/06 (2006.01) H04L 29/00 (2006.01) H04Q 7/20 (2006.01)

Patent

CA 2195489

An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.

L'invention est un appareil servant à améliorer la performance d'un récepteur sans fil de signaux numériques en salves; cet appareil comprend un circuit utilisé pour traiter une multiplicité de signaux reçus et fournir un signal traité, ainsi qu'un circuit de retardement servant à introduire un retard prédéterminé dans le signal traité. Le circuit de retardement est couplé au circuit de traitement. Le retard prédéterminé est tel que le signal traité est retardé pour correspondre avec une salve de données ultérieure. Le circuit de traitement pondère et combine les signaux reçus et réduit l'erreur quadratique moyenne du signal de sortie. Le circuit de traitement pondère et combine les signaux reçus en utilisant une configuration de symboles prédéterminée dans une séquence de synchronisation appartenant à une tranche de temps.

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