Isdn traffic generator adapter

Details Isdn traffic generator adapter Isdn traffic generator adapter

H - Electricity

04

J

379/3

H04J 3/14 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 1314337

ABSTRACT OF THE DISCLOSURE An ISDN traffic generator adapter is provided to couple an analog traffic generator which produces a plurality of commands and analog telephone signals to an ISDN switch. The traffic generator adapter includes a plurality of first circuits which couple the analog traffic generator to the ISDN switch. Each of these first circuits includes a plurality of tip/ring interface circuits, a processor and a plurality of S interface circuits. In particular, each of the tip/ring interface circuits can include means for detecting commands from the analog traffic generator and providing a message to the processor upon receipt of these commands. The tip/ring interface circuits further include an arrangement to convert the analog telephone signals from the traffic generator into ISDN B channel signals to be provided to the S interface circuits. The tip/ring interface circuits also include an arrangement to convert B channel signals received from the S interface circuitry into analog tip/ring signals to be provided to the traffic generator. The processor in each of said first circuits includes means to receive the messages from the tip/ring interface circuit and means for generating D channel signals to be provided to the S interface circuits. The processor also includes an arrangement to receive, act on and store D channel signals received from the ISDN switch through the S interface circuitry. Each of the S interface circuits includes an arrangement to combine the B channel signals received from the tip/ring interface with D channel signals from the processor to provide desired ISDN signals to the ISDN switch. Correspondingly, the S interface circuitry also includes means to receive ISDN signals from the switch and to provide B channel signals based thereon to the tip/ring interface circuitry and to provide D channel signals based thereon to the processor. In addition to the processor circuitry in the first circuits, a second processor circuit is provided which is coupled to the plurality of first circuits. The second processor includes an arrangement to selectively address individual ones of the processors of the first circuits. This can be used in conjunction with a D channel monitoring arrangement to control selection of predetermined ones of the processors of the first circuits so that D channel information from the ISDN switch stored in the selected processors can he individually monitored by the D channel monitor.

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