J-k flip flap utilizing current mode logic with...

Details J-k flip flap utilizing current mode logic with... J-k flip flap utilizing current mode logic with...

H - Electricity

03

K

328/127

H03K 19/003 (2006.01)

Patent

CA 1129017

ABSTRACT A 5-bit, J-K type master/slave edge triggered flip-flop register with buffered outputs is disclosed. Each J and K input is preceded by a two input AND gate to provide for greater design flexibility. In addition, provision has been made to reset all five flip-flop stages of the register synchronously as well as to configure the device as an inverting shift register for nonfunc- tional test (NFT) techniques. -2- 5202664

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