Jitter frequency shifting .delta.-.sigma. modulated signal...

H - Electricity – 04 – L

Patent

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Details

H04L 12/20 (2006.01) H03L 7/099 (2006.01) H03M 7/32 (2006.01) H03M 7/36 (2006.01) H04J 3/07 (2006.01) H04L 7/033 (2006.01) H03L 7/18 (2006.01)

Patent

CA 2316443

A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a "delta-sigma" (.DELTA.-.SIGMA.) modulator which functions as a voltage controller oscillator synchronizes the data rate of the output stream to that of the input stream in a manner which simplifies attenuation of fitter energy when the output data stream is desynchronized (demapped). The modulator generates an accurate pulse train by duty-cycle dithered modulation of the input stream, which the mapper interprets as stuff/null/de-stuff commands such that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.

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