Jitter reduction system in digital demultiplexers

Details Jitter reduction system in digital demultiplexers Jitter reduction system in digital demultiplexers

H - Electricity

04

J

H04J 3/02 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2145595

Comprising an elastic read-write memory subassembly (EM,WP,WA,RP,RA), whose read clock (RCK) varies its frequency with the signal obtained by a phase detector (PHC) as a function of the difference in time at which two pointers, for read (RP) and write (WP), take respective reference values. When the instant at which the write pointer (WP) takes the write reference value leads or lags by one write clock cycle (WCK) with respect to previous periods, this reference is increased or decreased in the same number of units, so that there is no abrupt change in the direct current component of the output signal of the phase detector (PHC); instead gradually and in fractions of the read reference, it is incremented or reduced in order to produce a smooth variation in the frequency of the read clock (RCK) that compensates the differences in net data output and input streams of the elastic memory (EM).

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