Keying signal generator with false output immunity

Details Keying signal generator with false output immunity Keying signal generator with false output immunity

H - Electricity

04

N

350/71

H04N 9/44 (2006.01)

Patent

CA 1163360

RCA 75,347 Abstract A circuit for generating a composite keying signal comprises a gate pulse generating circuit and a voltage translating network in a television receiver also including keyed video signal processing circuits. The composite keying signal comprises a first pulse developed by the translating network during horizontal blanking intervals of the video signal, and a second pulse developed by the gate circuit during a portion of the horizontal blanking intervals and superimposed on the first pulse. An output of the gate circuit is clamped during picture intervals to a fixed voltage via a low impedance clamping path that exhibits current conduction capability greater than the output current conduction capability of the gate pulse generating circuit. The clamping action prevents improper keying of the keyed circuits in response to false keying signals such as may be generated in response to spurious signals occurring during picture intervals of the television signal.

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