Latch strobe generator circuit

Details Latch strobe generator circuit Latch strobe generator circuit

G - Physics

06

F

324/58.1

G06F 11/00 (2006.01) G01R 13/00 (2006.01) G06F 3/147 (2006.01) G09G 3/04 (2006.01)

Patent

CA 1049098

Abstract of the Disclosure A delayed latch strobe generator for a display on a monitor used to service digital logic systems wherein time-based or event-based latch strobes are generated. A device on the monitor can be pre-set by a user to select the interval between the system latch strobe and the delayed latch strobe. When the normal latch strobe occurs, a binary counter is enabled. This counter is then incremented by system clock pulses. An exclusive- NOR comparator continually compares the counter contents with the setting of the user-controlled device. A match, which indicates the interval has elapsed, results in the generation of a delayed latch strobe which is applied to the display.

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