Latch-up free power mos-bipolar transistor

Details Latch-up free power mos-bipolar transistor Latch-up free power mos-bipolar transistor

H - Electricity

01

L

H01L 29/73 (2006.01) H01L 29/24 (2006.01)

Patent

CA 2286699

A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into whole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

L'invention concerne un transistor bipolaire MOS qui comporte un transistor bipolaire NPN à carbure de silicium formé sur un substrat non épitaxié en carbure de silicium de type N à cristal unique, avec une couche de migration de type N et une couche de base de type P. De préférence, la couche de base est formée par croissance épitaxiale et constituée en structure mésa. Un transistor NMOS au carbure de silicium est formé en position adjacente au transistor bipolaire NPN, de sorte que la tension appliquée à la grille du premier fasse passer le second à l'état passant. Le transistor NMOS a une source et un drain conçus pour fournir un courant de base au transistor bipolaire NPN lorsque ce dernier est à l'état passant. L'invention concerne également un système permettant de convertir un courant d'électrons circulant entre la source et le drain en courant de trous afin de l'injecter dans la couche de base de type P. On peut aussi mettre en place un système permettant de diminuer la formation de champs localisés associée à une couche d'isolation du transistor NMOS considéré.

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