Latchup and electrostatic discharge protection structure

H - Electricity – 01 – L

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356/66

H01L 29/66 (2006.01) H01L 27/02 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1289267

ABSTRACT Latchup and electrostatic discharge protection apparatus for a silicon integrated circuit CMOS inverter having parasitic bipolar elements, and having integrated diode apparatus connected between an input to the inverter and positively and negatively poled power terminals, the integrated circuit having an N- doped substrate, and one of the diodes formed of a P- doped well extending into the substrate from a surface of the substrate, a first N+ doped region extending into the P- doped well and apparatus for connecting the input to the inverter to the N+ doped region, comprised of a second N+ doped region, spaced from the first N+ region by an insulating apparatus extending above the surface of the substrate, which extends into the P- doped well, a conductive field plate extending over the insulating apparatus and in contact with the input to form an N field device with the first and second N+ doped regions, apparatus for applying positively poled power to the second N+ doped region, a P+ doped region adjacent the first N+ doped region extending into the P- well from the surface of the substrate, and conductive apparatus connecting the first N+ doped region and the P+ doped region together at an upper surface thereof.

547801

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