Latchup-preventing cmos device and method for fabricating same

Details Latchup-preventing cmos device and method for fabricating same Latchup-preventing cmos device and method for fabricating same

H - Electricity

01

L

356/162

H01L 29/76 (2006.01) H01L 21/461 (2006.01)

Patent

CA 1232084

- 21 - LATCHUP-PREVENTING CMOS DEVICE AND METHOD FOR FABRICATING SAME Abstract A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 µm, as well as a method for fabricating the device is disclosed. The inventive CMOS device includes a latchup- preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 µm, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than! or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

464876

Affiliated with

Also associated with

Rating

Latchup-preventing cmos device and method for fabricating same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latchup-preventing cmos device and method for fabricating same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latchup-preventing cmos device and method for fabricating same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1203891