Layered chip structure

Details Layered chip structure Layered chip structure

H - Electricity

05

K

H05K 3/46 (2006.01) H01L 21/00 (2006.01) H01L 21/48 (2006.01)

Patent

CA 2132747

2132747 9319857 PCTABS00027 A method for making a substrate for use in a multilayered integrated circuit or multichip module which includes coating a conductive material (14) on a surface of a support sheet (10) to form a conductive circuit (12) and then drying the sheet. Next, a coating of a layer of dielectric layer (18) is placed on the support surface in the areas where the conductive material is not cast. After which the coated sheet is densified to form a densified conductive circuit embedded dielectric layer. A second coating of a dielectric (28) is placed over the first densified conductive circuit embedded dielectric layer such that the second layer is characterized by vias (30) therein which are in register with at least a portion of the conductive circuit (12). The vias in the second dielectric layer are filled to form electrically conductive vias and then densified to form the substrate (44).

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