Ldpc decoding methods and apparatus

Details Ldpc decoding methods and apparatus Ldpc decoding methods and apparatus

H - Electricity

03

M

H03M 13/13 (2006.01) H04W 88/02 (2009.01)

Patent

CA 2672074

A flexible and relatively hardware efficient LDPC decoder (900) is described. The decoder cai be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process (901). Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths (912) are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor (908) that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused (916).

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