Level sensitive reset circuit for digital logic

Details Level sensitive reset circuit for digital logic Level sensitive reset circuit for digital logic

H - Electricity

03

K

328/114.1

H03K 17/78 (2006.01) G06F 1/24 (2006.01) H03K 17/22 (2006.01) H03K 17/795 (2006.01) H03K 19/003 (2006.01) H03K 21/38 (2006.01)

Patent

CA 1195739

ABSTRACT A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip- flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is termi- nated.

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