Linear array wafer scale integration architecture

Details Linear array wafer scale integration architecture Linear array wafer scale integration architecture

H - Electricity

03

K

328/127, 356/30

H03K 19/08 (2006.01) G11C 29/00 (2006.01) H03K 19/0175 (2006.01) H03K 19/173 (2006.01)

Patent

CA 2015853

A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplex- ers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the bound- ary adjacent to that with which the multiplexer is asso- ciated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

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