Load sharing system and a method for processing of data and...

G - Physics – 06 – F

Patent

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Details

G06F 9/46 (2006.01) G06F 15/163 (2006.01)

Patent

CA 2202974

The present invention relates to a system and a method respectively for processing of data comprising a central processor system comprising at least one signal processor (SPU) for processing and administrating signals and at least one executing processor (IPU) comprising a multiport process register memory (RM). The signal processor (SPU) and the executing processor (IPU) cooperate and the system further comprises a system memory (SM). At least one traffic handling program level (THL, BAL) of the system comprises at least two identical register sets in the register memory (RM) of the executing processor which comprises at least one signal input port (A), a signal output port (B) and a data access port (C). Signal data transportations between the signal processor (SPU) and the executing processor (IPU) are done by the signal processor (SPU) during execution. The execution processor (IPU) directly switches from execution of one job to another job through switching register sets.

L'invention concerne un système et un procédé de traitement de données. Le système comprend un processeur central doté d'au moins un processeur de signaux (SPU) qui traite et administre des signaux, et au moins un processeur d'exécution (IPU) qui comporte une mémoire multiport de registre (RM) de processus. Le processeur de signaux (SPU) et le processeur d'exécution (IPU) coopèrent et le système comprend aussi une mémoire de système (SM). Dans ce système, un niveau de programme de traitement (THL, BAL) de trafic au moins comprend au moins deux jeux de registres identiques placés dans la mémoire de registre (RM) du processeur d'exécution qui présente au moins un port d'entrée de signal (A), un port de sortie de signal (B) et un port d'accès de données (C). Les transferts de données de signaux entre le processeur de signal (SPU) et le processeur d'exécution (IPU) sont effectués par le processeur de signaux (SPU) pendant l'exécution. Le processeur d'exécution (IPU) passe directement de l'exécution d'une tâche à une autre en changeant de jeux de registres.

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