Logic array having improved speed characteristics

G - Physics – 11 – C

Patent

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352/82.3

G11C 11/40 (2006.01) G11C 5/06 (2006.01) G11C 17/12 (2006.01) H01L 27/112 (2006.01)

Patent

CA 1135859

- 1 - ABSTRACT: An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of simi- larly improved logic arrays. The ROM includes parallel rows of con- ductors oriented normal to parallel doped regions which form column conductors. The ROM is implemented with field-effect transistors and comprises two decoder fields and a data field. The transistors of the decoder fields serve to define open circuits between adjacent column conductors in accordance with binary input signals applied to the decoder fields. In the illustrative ROM, a first column con- ductor is connected to a return terminal of a power supply and a second column conductor is connected to a "pull-up" circuit. The il- lustrative circuit provides for the connection of power supply return connections to both ends of the one column conductor and provides for the connection of pull-up circuits to both ends of the second column conductor. The row conductors are connected to gates of transistors in both the data and the decoder fields and a low impedance path from the pull-up circuits to the power supply return is established in response to signals on the row conductors.

330506

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