Logic array with testing circuitry

Details Logic array with testing circuitry Logic array with testing circuitry

G - Physics

06

F

324/58.1

G06F 11/00 (2006.01) G01R 31/3185 (2006.01) G06F 11/10 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1040270

ABSTRACT This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. During testing, a gating signal to each of the decoders is used to couple the interrogatior signals of one of these decoders at a time to the input lines of the array. This allows the interrogation of one input line at a time and the detection of the output signals produced by that inter- rogation on the output lines of the array. To determine whether the output signals are proper, the array contains one or more additional output lines which contain parity or check bits on the circuit elements arranged along each of the input lines. When an input line is inter- rogated the output signals including those produced by the parity or check bits are exclusively OR'd to determine if the interrogated input line contains the proper number of circuit elements. This circuitry eliminates the need for storing information as to logic functions per- formed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.

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