Logic duplication method for reducing circuit size and delay...

Details Logic duplication method for reducing circuit size and delay... Logic duplication method for reducing circuit size and delay...

H - Electricity

05

K

H05K 1/02 (2006.01) G06F 17/50 (2006.01) H01L 27/02 (2006.01) H05K 3/00 (2006.01)

Patent

CA 2054290

LOGIC DUPLICATION METHOD FOR REDUCING CIRCUIT SIZE AND DELAY TIME Steven J. Perry ABSTRACT OF THE DISCLOSURE: Elements within a logic design which have a fan-out count greater than one are duplicated in order to reduce circuit size and/or minimize signal propagation time.

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