Logic level translator or cml-t2l used in all cml technoloy

Details Logic level translator or cml-t2l used in all cml technoloy Logic level translator or cml-t2l used in all cml technoloy

G - Physics

06

F

354/111

G06F 5/00 (2006.01) H03K 19/018 (2006.01)

Patent

CA 1085515

LOGIC LEVEL TRANSLATOR Abstract of the Disclosure A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, therby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

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