G - Physics – 06 – F
Patent
G - Physics
06
F
354/120
G06F 17/50 (2006.01)
Patent
CA 1287174
Abstract of the Disclosure An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.
580777
International Business Machines Corporation
Na
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