Long range ordered and epitaxial oxides including sio2, on...

Details Long range ordered and epitaxial oxides including sio2, on... Long range ordered and epitaxial oxides including sio2, on...

H - Electricity

01

L

H01L 21/316 (2006.01) H01L 21/04 (2006.01) H01L 21/28 (2006.01) H01L 21/306 (2006.01)

Patent

CA 2311766

A semiconductor processing method capable of producing highly ordered, ultra thin dielectrics, including gate oxide and other semiconductor dielectrics, and interphase phases with low defect density. The process includes a degrease step (21), an etch (22), a primary oxidation (24), and then a passivation step (26) which utilizes hydrofluoric acid to passivate the cleaned silicon surface with hydrogen. Dielectric layers may then be formed with low interface defect density, low flat-band voltages, and low fixed charge on semiconductor substrates. Ultra-thin layers of between 1/2 to 10 nm and thicker have been formed on Si(100). Devices, dielectrics and interphase phases formed using this process are claimed as well.

L'invention concerne un procédé de traitement d'un semiconducteur capable de traiter des diélectriques ultra minces, d'un ordre élevé, comprenant un oxyde de grille, d'autres diélectriques de semi-conducteurs et des phases d'interphase à faible densité de défauts. Ce procédé permet de former des couches diélectriques avec une faible densité de défauts d'interface, des tensions basses plates et une charge fixe faible sur Si, Si¿x?Ge¿1-x?, GaAs, Si¿1-x-y? Ge¿x?C¿y?, Si¿3(1-x)?Ge¿3x?N¿4(1-.delta.)?, Ge, Ga¿1-x?Al¿x?As, Si¿x?Ge¿(1-x)?(O¿y?N¿1-y?)¿n?, Si¿1-x-y?Ge¿x?C¿y?(O¿z?N¿1-z?)¿n? et (Si¿1-x-y?Ge¿x?C¿y?)¿3?N¿4-x-y?. Des couches ultra minces présentant une épaisseur comprise entre 0,5 et 10nm et plus épaisses ont été formées sur Si(100). L'invention concerne également des dispositifs, des diélectriques et des phases d'interphase formées à l'aide de ce procédé.

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